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rt8800/b 1 ds8800/b-08 april 2011 www.richtek.com general description the rt8800/b are general purpose multi-phase synchronous buck controllers dedicating for high density power supply regulation. the parts implement 2, and 3 buck switching stages operating in interleaved phase set automatically. the output voltage is regulated and controlled following the input voltage of fb pin. with such a single analog control, the rt8800/b provide a simple, flexible, wide-range and extreme cost-effective high- density voltage regulation solutions for various high-density power supply application. the rt8800/b multi-phase architecture provide high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. the high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. rt8800/b implement both voltage and current loops to achieve good regulation, response and power stage thermal balance. the rt8800/b apply the time sharing dcr current sensing technology newly as well; with such a topology, the rt8800/b extract the dcr of output inductor as sense component to deliver a more precise load line regulation and better thermal balance capability. moreover, the parts monitor the output voltage for over- current and over-voltage protection; soft-start and programmable under-voltage lockout are also provided to assure the safety of power system. features z z z z z 5v power supply voltage z z z z z 2/3-phase power conversion with automatic phase selection (rt8800 : 2/3-phase, RT8800B : 2-phase) z z z z z output voltage controlled by external reference voltage z z z z z precise core voltage regulation z z z z z power stage thermal balance by dcr current sensing z z z z z extreme low-cost, lossless time sharing current sensing z z z z z internal soft-start z z z z z hiccup mode over-current protection z z z z z over-voltage protection z z z z z adjustable operating frequency and typical at 300khz per phase z z z z z power good indication z z z z z small 16-lead vqfn package (for rt8800 only) z z z z z rohs compliant and 100% lead (pb)-free applications z desktop cpu core power z low output voltage, high power density dc-dc converters z voltage regulator modules general purpose 2/3-phase pwm controller for high-density power supply marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. package type qv : vqfn-16l 3x3 (v-type) s : sop-16 lead plating system p : pb free g : green (halogen free and pb free) rt8800/b 2-phase 2/3-phase
rt8800/b 2 ds8800/b-08 april 2011 www.richtek.com pin configurations (top view) vqfn-16l 3x3 rt8800 sop-16 RT8800B functional pin description dacfb negative input of internal buffer amplifier for reference voltage regulation. the pin voltage is locked at internal v ref = 0.8v by properly close the buffer amplifier feedback loop. dacq the pin is defined as the output of internal buffer amplifier for reference voltage regulation. fb the pin is defined as the inverting input of internal error amplifier. dvd the pin is defined as a programmable power uvlo detection input. trip threshold = 0.8v at v dvd rising. comp the pin is defined as the output of the error amplifier and the input of all pwm comparators. pi the pin is defined as the positive input of the error amplifier. rt switching frequency setting. connect this pin to gnd with a resistor to set the frequency. icommon common negative input of current sense amplifiers for all three channels. pgood output power-good indication. the signal is implemented as an output signal with open-drain type. isp1 , isp2 , isp3 current sense positive inputs for individual converter channel current sense. pwm1 , pwm2 , pwm3 pwm outputs for each phase switching drive. vdd chip power supply. connect this pin to a 5v supply. gnd chip power ground. exposed pad (17) (rt8800) the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. dacfb isp1 pgood isp3 isp2 dvd fb dacq icommon comp pi rt pwm1 vdd pwm3 pwm2 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd 17 vdd dacfb dacq fb dvd comp pi rt icommon gnd pgood isp 2 isp 1 n/c pwm1 pwm2 2 9 8 7 6 5 4 3 10 16 15 14 13 12 11
rt8800/b 3 ds8800/b-08 april 2011 www.richtek.com typical application circuit (note : the inductor? s dcr value must be large than 0.3m : x7r/r-type capacitor is required for all time constant setting capacitor of dcr sensing.) boot1 ugate1 phase1 lgate1 vdd pvcc pwm1 pwm2 rt9602 11 14 5 1 2 4 13 12 ugate2 phase2 lgate2 boot2 gnd pgnd ss12/sm 10 1uf 12v 1uf phb83n03lt phb95n03lt 1uf 2200uf 12v 7 8 9 phb83n03lt phb95n03lt 1uf 2200uf ss12/sm 1uf v core 3 6 10 3.3nf 2.2 0 0 0 0 2.2 3.3nf 0.5uh 0.5uh 1uh phase2 phase1 10uf x 4 1000uf x 12 phase2 phase1 pi dacq dacfb pgood pwm2 isp2 fb comp vdd pwm1 rt dvd icommon isp1 vid0 vid2 vid3 vid4 vid1 vid5 3.3v 12v v core 5v 11 4 6 5 8 3 9 13 12 16 15 1 2 7 15k 10nf 33pf 3k 0 0 optional optional 1uf 1uf 430 3k 16k 27k 10k 1.8k 110k 56k 27k 13k 6.8k 3.3k r r RT8800B 5.1k gnd 10 optional for r & c 1uf 1000uf optional r droop r icommon1 r icommon2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 c1 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 to c29 c30 to c33 d1 d2 q1 q2 q3 q4 q5 q6 l1 l2 l3 c2 figure a. 2-phase with resistive dac
rt8800/b 4 ds8800/b-08 april 2011 www.richtek.com phase3 phase2 phase1 pi dacq dacfb pgood pwm3 pwm2 isp3 isp2 fb comp vdd pwm1 rt dvd icommon isp1 vid0 vid2 vid3 vid4 vid1 vid5 3.3v 12v v core 5v 9 3 5 4 7 2 8 12 11 10 14 15 13 16 1 6 gnd 15k 10nf 33pf 3k 4.7uf optional optional optional 1uf 1uf 1uf 430 3k 16k 27k 10k 1.8k 110k 56k 27k 13k 6.8k 3.3k r r r rt8800 5.1k boot2 pwm3 pwm2 pwm1 boot1 lgate3 pvcc3 phase3 ugate3 boot3 ugate2 pvcc2 phase2 lgate2 nc ugate1 pvcc1 phase1 lgate1 vdd 12v 5v sb phase1 v in phase2 v core phase3 1242223 9 10 11 15 14 3 8 20 21 19 17 16 7 5 4 2 gnd 12v 12v 12v v in 12v 1uf 1000uf 1uh 0 1uf 1uf 0 10 1uf 3.3nf 2.2 1uf 0 1uf 0 3.3uf 2.2 0.5uh 0.5uh 0.5uh 1uf 0 3.3nf 2.2 0 1uf 10uf x 4 1000uf x 12 rt9605 1500uf x 4 12v v in optional optional r droop r icommon1 r icommon2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 c1 c2 c3 c4 c8 c9 c10 to c13 c5 c6 c7 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 to c35 c36 to c39 d1 d2 d3 q1 q2 q3 q4 q5 q6 q7 q8 q9 l1 l2 l3 figure b. 3-phase with resistive dac
rt8800/b 5 ds8800/b-08 april 2011 www.richtek.com phase3 phase2 phase1 pi dacq dacfb pgood pwm3 pwm2 isp3 isp2 fb comp vdd pwm1 rt dvd icommon isp1 3.3v 12v v core 5v 9 3 5 4 7 2 8 12 11 10 14 15 13 16 1 6 gnd 15k 10nf 33pf 3k 4.7uf optional optional optional 1uf 1uf 1uf 430 3k 16k 27k 10k 5.1k r r r rt8800 boot2 pwm3 pwm2 pwm1 boot1 lgate3 pvcc3 phase3 ugate3 boot3 ugate2 pvcc2 phase2 lgate2 nc ugate1 pvcc1 phase1 lgate1 vdd 12v 5v sb phase1 v in phase2 v core phase3 1242223 9 10 11 15 14 3 8 20 21 19 17 16 7 5 4 2 gnd 12v 12v 12v v in 12v 1uf 1000uf 1uh 0 1uf 1uf 0 10 1uf 3.3nf 2.2 1uf 0 1uf 0 3.3uf 2.2 0.5uh 0.5uh 0.5uh 1uf 0 3.3nf 2.2 0 1uf 10uf x 4 1000uf x 12 rt9605 1500uf x 4 12v v in optional optional r droop r icommon1 r icommon2 5.1k 10nf rt9401a/b vid1 vdd vid0 vid3 vda gnd vid2 vid4 5v 1 2 3 4 5 6 7 8 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 to c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 to c36 c37 to c40 d1 d2 q1 q2 q3 q4 q5 q6 q7 q8 q9 l1 l2 l3 figure c. 3-phase with rt9401a/b dac generator
rt8800/b 6 ds8800/b-08 april 2011 www.richtek.com function block diagram oscillator & ramp generator + + + + + + sample & hold pwm1 pwm2 pwm3 ocp sum/n & ocp detection pgood dvd gnd soft start + + - icommon isp 1 isp 2 isp 3 pwm logic & driver pwmcp + - pwm logic & driver pwmcp + - pwm logic & driver pwmcp + - + + + mux mux sample & hold sample & hold vdd fb ea gm comp - + - 0.8v v ref pi buffer amplifier inh inh inh power on reset rt maj 500mv ovp dacfb dacq
rt8800/b 7 ds8800/b-08 april 2011 www.richtek.com vid5 vid4 vid3 vid2 vid1 vid0 nominal output voltage (v) 1 1 1 1 1 1 1.0800 1 1 1 1 1 0 1.1000 0 1 1 1 1 0 1.1125 1 1 1 1 0 1 1.1250 0 1 1 1 0 1 1.1375 1 1 1 1 0 0 1.1500 0 1 1 1 0 0 1.1625 1 1 1 0 1 1 1.1750 0 1 1 0 1 1 1.1875 1 1 1 0 1 0 1.2000 0 1 1 0 1 0 1.2125 1 1 1 0 0 1 1.2250 0 1 1 0 0 1 1.2375 1 1 1 0 0 0 1.2500 0 1 1 0 0 0 1.2625 1 1 0 1 1 1 1.2750 0 1 0 1 1 1 1.2875 1 1 0 1 1 0 1.3000 0 1 0 1 1 0 1.3125 1 1 0 1 0 1 1.3250 0 1 0 1 0 1 1.3375 1 1 0 1 0 0 1.3500 0 1 0 1 0 0 1.3625 1 1 0 0 1 1 1.3750 0 1 0 0 1 1 1.3875 1 1 0 0 1 0 1.4000 0 1 0 0 1 0 1.4125 1 1 0 0 0 1 1.4250 0 1 0 0 0 1 1.4375 1 1 0 0 0 0 1.4500 0 1 0 0 0 0 1.4625 1 0 1 1 1 1 1.4750 0 0 1 1 1 1 1.4875 1 0 1 1 1 0 1.5000 0 0 1 1 1 0 1.5125 1 0 1 1 0 1 1.5250 0 0 1 1 0 1 1.5375 1 0 1 1 0 0 1.5500 table. output voltage program to be continued
rt8800/b 8 ds8800/b-08 april 2011 www.richtek.com vid5 vid4 vid3 vid2 vid1 vid0 nominal output voltage (v) 0 0 1 1 0 0 1.5625 1 0 1 0 1 1 1.5750 0 0 1 0 1 1 1.5875 1 0 1 0 1 0 1.6000 1 0 1 0 0 1 1.6250 1 0 1 0 0 0 1.6500 1 0 0 1 1 1 1.6750 1 0 0 1 1 0 1.7000 1 0 0 1 0 1 1.7250 1 0 0 1 0 0 1.7500 1 0 0 0 1 1 1.7750 1 0 0 0 1 0 1.8000 1 0 0 0 0 1 1.8250 1 0 0 0 0 0 1.8500 table. output voltage program note: 1 : open 0 : v ss or gnd
rt8800/b 9 ds8800/b-08 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply voltage, v dd ------------------------------------------------------------------------------------------- 7v z input, output or i/o voltage ---------------------------------------------------------------------------------- gnd ? 0.3v to v dd + 0.3v z power dissipation, p d @ t a = 25 c vqfn-16l 3x3 -------------------------------------------------------------------------------------------------- 1.47w sop-16 ----------------------------------------------------------------------------------------------------------- 1w z package thermal resistance (note 2) vqfn-16l 3x3, ja --------------------------------------------------------------------------------------------- 68 c/w sop-16, ja ----------------------------------------------------------------------------------------------------- 100 c/w z junction temperature ------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------- 200v electrical characteristics (v dd = 5v, t a = 25c, unless otherwise specified) parameter symbol test conditions min typ max unit v dd supply current nominal supply current i dd pwm 1,2,3 open -- 5 -- ma power on reset rising 4.0 4.2 4.5 v dd threshold hysteresis 0.2 0.5 -- v dvd rising threshold 0.75 0.8 0.85 v dvd hysteresis -- 65 -- mv oscillator free running frequency f osc r rt = 16k 170 200 230 khz frequency adjustable range f osc_adj 50 -- 400 khz ramp amplitude v osc r rt = 16k -- 1.7 -- v ramp valley v rv -- 1.0 -- v maximum on-time of each channel 62 66 75 % minimum on-time of each channel -- 120 -- ns rt pin voltage v rt r rt = 16k 0.77 0.82 0.87 v recommended operating conditions (note 4) z supply voltage, v dd ------------------------------------------------------------------------------------------- 5v 10% z ambient temperature range --------------------------------------------------------------------------------- 0 c to 70 c z junction temperature range --------------------------------------------------------------------------------- 0 c to 125 c to be continued
rt8800/b 10 ds8800/b-08 april 2011 www.richtek.com parameter symbol test conditions min typ max unit reference voltage reference voltage v dacfb 0.79 0.8 0.81 v dacfb sourcing capab ility -- -- 10 ma error amplifier dc gain -- 65 -- db gain-bandwidth product gbw c l = 10pf -- 10 -- mhz slew rate sr c l = 10pf -- 8 -- v/ s current sense gm amplifier recommended full scale source current -- 100 -- a ocp trip level i oc p 160 190 220 a protection over-voltage trip (v fb - v dacq ) -- 500 -- mv power good pgood output low voltage v pgood i pgood = 4ma -- -- 0.2 v pgood delay t pgood_delay 90% * v out to pgood_h 4 -- 8 ms note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt8800/b 11 ds8800/b-08 april 2011 www.richtek.com typical operating characteristics v ref vs. temperature 0.78 0.785 0.79 0.795 0.8 0.805 0.81 0.815 -25 -10 5 20 35 50 65 80 95 110 125 temperature v ref (v) ( c) gm3 gm2 gm1 r icommon1 = 430 frequency vs. r rt 0 100 200 300 400 500 600 700 800 900 1000 0 5 10 15 20 25 30 35 40 45 50 55 60 r rt (k [ ) frequency (khz) (k ) load line 1.24 1.26 1.28 1.3 1.32 1.34 1.36 1.38 1.4 0 102030405060708090100 output current (a) output voltage (v) r ll = 1.5m , r icommon2 = 10k , r droop = 100 v in = 12v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 102030405060708090100 output current (a) efficiency (%) driver rt9605 v in = 12v, v out = 1.4v gm 0 10 20 30 40 50 60 70 80 90 0 102030405060708090100110 v c (mv) i adj (ua) gm3 gm2 gm1 r icommon1 = 430 ( c) ocp trip point vs. temperature 0 30 60 90 120 150 180 210 240 -25-10 5 203550658095 temperature ix (ua)
rt8800/b 12 ds8800/b-08 april 2011 www.richtek.com frequency vs. temperature 0 50 100 150 200 250 300 350 -25 -10 5 20 35 50 65 80 95 110 125 temperature frequency (khz) ( c) r rt = 16k time (2.5 s/div) load transient response ugate1 (20v/div) v core (200mv/div) ugate2 (20v/div) ugate3 (20v/div) phase 1, i out = 5a to 85a @sr = 93a/us) time (2.5 s/div) load transient response ugate1 (20v/div) v core (200mv/div) ugate2 (20v/div) ugate3 (20v/div) phase 3, i out = 5a to 85a @sr = 93a/us) time (10ms/div) over current protection i l1 +i l2 (50a/div) v core (1v/div) pwm1 (10v/div) v comp (2v/div) short while turn_on time (10ms/div) over current protection i l1 +i l2 (50a/div) v comp (2v/div) pwm1 (10v/div) v core (1v/div) short after turn_on time (2.5 s/div) load transient response ugate1 (20v/div) v core (200mv/div) ugate2 (20v/div) ugate3 (20v/div) phase2, i out = 5a to 85a @sr = 93a/us)
rt8800/b 13 ds8800/b-08 april 2011 www.richtek.com time (10 s/div) v id on the fly rising i out = 5a v fb (200mv/div) v id0 (2v/div) pwm (5v/div) v core (200mv/div) time (10 s/div) v id on the fly rising i out = 90a v fb (200mv/div) v id0 (2v/div) pwm (5v/div) v core (200mv/div) time (25 s/div) v id on the fly falling v fb (200mv/div) v id0 (2v/div) pwm (5v/div) v core (50mv/div) i out = 90a time (25 s/div) v id on the fly falling v fb (200mv/div) v id0 (2v/div) pwm (5v/div) v core (100mv/div) i out = 5a
rt8800/b 14 ds8800/b-08 april 2011 www.richtek.com application information rt8800/b are multiphase dc/dc controllers for extreme low cost applications that precisely regulate cpu core voltage and balance the current of different power channels using time sharing current sensing method. the converter consisting of rt8800/b and its companion mosfet driver rt96xx series provide high quality cpu power and all protection functions to meet the requirement of modern vrm. phase setting and converter start up rt8800/b interface with companion mosfet drivers (like rt9602, rt9603, and rt9605) for correct converter initialization. rt8800/b will sense the voltage on pwm pins at the instant of por rising. if the voltage is smaller than (v dd ? 1.2v) the related channel is activated. tie the pwm to v dd and the corresponding current sense pins to gnd or left float if the channel is unused. for example, for 2-channel application, tie pwm3 to v dd and isp3 to gnd (or let isp3 open). pgood function and soft start to indicate the condition of multiphase converter, rt8800/b provide pgood signal through an open drain connection. the output becomes high impedance after internal ss ramp > 3.5v. 1) mode 1 (ss< vramp_valley) initially the comp stays in the positive saturation. when ss< v ramp_valley , there is no non-inverting input available to produce duty width. so there is no pwm signal and v out is zero. 2) mode 2 (v ramp_valley < ss< cross-over) when ss>v ramp_valley , ss takes over the non-inverting input and produce the pwm signal and the increasing duty width according to its magnitude above the ramp signal. the output follows the ramp signal, ss. however while v out increases, the difference between v out and sse(ss ? v gs ) is reduced and comp leaves the saturation and declines. the takeover of ss lasts until it meets the comp. during this interval, since the feedback path is broken, the converter is operated in the open loop. 3) mode3 ( cross-over< ss < v gs + v ref ) when the comp takes over the non-inverting input for pwm amplifier and when sse (ss ? v gs ) < v ref , the output of the converter follows the ramp input, sse (ss ? v gs ). before the crossover, the output follows ss signal. and when comp takes over ss, the output is expected to follow sse (ss ? v gs ). therefore the deviation of v gs is represented as the falling of v out for a short while. the comp is observed to keep its decline when it passes the cross-over, which shortens the duty width and hence the falling of v out happens. since there is a feedback loop for the error amplifier, the output ? s response to the ramp input, sse (ss ? v gs ) is lower than that in mode 2. 4) mode 4 (ss > v gs + v ref ) when ss > v gs + v ref , the output of the converter follows the desired v ref signal and the soft start is completed now. voltage control the voltage control loop consists of error amplifier, multiphase pulse width modulator, driver and power components. as conventional voltage mode pwm controller, the output voltage is locked at the positive input of error amplifier and the error signal is used as the control signal of pulse width modulator. the pwm signals of different channels are generated by comparison of ea output and split-phase sawtooth wave. power stage transforms v in to output by pwm signal on-time ratio. output voltage program the output voltage of a rt8800/b converter is programmed to discrete levels between 1.08v and 1.85v. the voltage identification (v id ) pins program an external voltage reference (dacq) with a 6-bit digital-to-analog converter (dac). the level of dacq also sets the ovp threshold. the output voltage should not be adjusted while the converter is delivering power. remove input power before comp v core sse_internal ss_internal cross-over v ramp_valley
rt8800/b 15 ds8800/b-08 april 2011 www.richtek.com dac design guideline in high temperature environment, v core becomes unstable for the leakage current in vid pins is increasing. the leakage will increase current consumption of cpu, and then raise rt8800's v dacq reference output, so does v core voltage. below are four comparison charts for different cpus. note: in below figure 2 to figure 5, the original r means the resister values shown in typical application circuit. r=1/3 and r=1/9 mean that the original r is divided by 3 or 9. figure 5 figure 4 v core vs. temperature 1.335 1.34 1.345 1.35 1.355 1.36 1.365 1.37 1.375 1.38 30 35 40 45 50 55 60 65 70 temperature v core (v) ( c) cpu : p4-2.8g v core = 1.35v r = 1/9 r = 1/3 the original r figure 3 figure 2 changing the output voltage. adjusting the output voltage during operation may trigger the over-voltage protection. the dac function is a precision non-inverting summation amplifier shown in figure 1. the resistor values shown are only approximations of the actual precision values used. grounding any combination of the v id pins increases the dacq voltage. the ? open ? circuit voltage on the v id pins is the band gap reference voltage (v ref = 0.8v). + - v ref (0.8v) v dacfb op v dacq rf rg vid0 vid1 vid2 vid3 vid4 vid5 r r r r r r figure 1. the structure of discrete dac generator v core vs. temperature 1.54 1.55 1.56 1.57 1.58 1.59 1.6 1.61 1.62 1.63 1.64 30 35 40 45 50 55 60 65 70 temperature v core (v) ( c) cpu : p4-3.2g v core = 1.55v r = 1/9 r = 1/3 the original r v core vs. temperature 1.54 1.56 1.58 1.6 1.62 1.64 1.66 1.68 30 35 40 45 50 55 60 65 70 temperature v core (v) ( c) cpu : p4-3.06g v core = 1.55v r = 1/9 r = 1/3 the original r v core vs. temperature 1.52 1.54 1.56 1.58 1.6 1.62 1.64 1.66 30 35 40 45 50 55 60 65 70 temperature v core (v) ( c) cpu : celeron 2.0g v core = 1.55v r = 1/9 r = 1/3 the original r
rt8800/b 16 ds8800/b-08 april 2011 www.richtek.com figure 9 is the test circuit for gm. we apply test signal at gm inputs and observe its signal process output by pi pin sinking current. figure 10 shows the variation of signal processing of all channels. we observe zero offsets and good linearity between phases. icommon1 c x l c r v i i dcr v c r dcr l = = = current sensing setting rt8800/b senses the current flowing through inductor via its dcr for channel current balance and droop tuning. the differential sensing gm amplifier converts the voltage on the sense component (can be a sense resistor or the dcr of the inductor) to current signal into internal circuit (see figure 7). figure 7. current sense circuit l dcr r r icommon gmx i x c + - i l v c +- figure 9. the test circuit of gm pwm signal & high side mosfet gate signal low side mosfet gate signal inductor current falling slope = vo/l i l i l(avg) i l(s/h) figure 8. inductor current and pwm signal s in o in off off o l(avg) l(s/h) icommon1 l(s/h) x(s/h) t x ) v v - v ( t 2 t x l v - i i ; r dcr x i i = = = in order to maintain the v dacq within 1% tolerance in the worst case, the total driver current of the dac regulator should support up to 40ma. as the design of rt8800/b, the maximum driving current of the internal op is 10ma. as shown in figure 6, we suggest to add an external transistor 2n3904 for higher current for v dac regulation. + - v ref (0.8v) vdacfb op pi 43 121 vid0 vid1 vid2 vid3 vid4 vid5 1.34k 645 310 162 81 2.63k v cc q1 2n3904 vdacq figure 6. immune circuit against cpu leakage current icommon1 s in o in o l(avg) x(s/h) s r dcr x 2l t x ) v v - v ( - v - i i t period switching, for ? ? ? ? ? ? ? ? ? ? ? ? = = the sensing circuit gets by local feedback. i x is sampled and held just before low side mosfet turns off (figure 8). icommon1 l x r dcr x i i = l dcr esr r icommon1 1k gmx i x v c + - v ispx v icommon c +-
rt8800/b 17 ds8800/b-08 april 2011 www.richtek.com figure 10. the linearity of gmx gm 0 10 20 30 40 50 60 70 0 20406080100 v c (mv) i adj (ua) gm1 gm2 gm3 figure 11 shows the time sharing technique of gm amplifier. we apply test signal at phase 3 and observe the waveforms at both pins of gm amplifier. the waveforms show time sharing mechanism and the perfomance of gm to hold both input pins equal when the shared time is on. figure 11 time sharing of gm time (1 s/div) pwm3 v isp3 and v i common ch1:(2v/div) ch2:(50mv/div) ch3:(50mv/div) v isp3 v icommon current ratio setting for some case with preferable current ratio instead of current balance, the corresponding technique is provided. due to different physical environment of each channel, it is necessary to slightly adjust current loading between channels. figure 12. shows the application circuit of gm for current ratio requirement. applying kvl along l+dcr branch and r1+c//r2 branch: look for its corresponding conditions: figure 12. application circuit for current ratio setting l c c c c c c l l i x dcr r2 r1 r2 v for v r2 r2 r1 dt dv c x r1 v dt dv c r2 v r1 i x dcr dt di l + = + + = + ? ? ? ? ? ? + = + c x (r1//r2) dcr l let i x dcr dt di x dcr x c x (r1//r2) i x dcr dt di l l l l l = + = + figure 13. gm3 setting for current ratio function figure 14. gm1,2 setting for current ratio function l c i x dcr x r2 r1 r2 v then c x (r1//r2) dcr l if thus + = = with internal current balance function, this phase would share (r 1 +r 2 )/r 2 times current than other phases. figure 13 &14 show different settings for the power stages. i l 1.5uh 1m 3k 1uf 3k 1.5uh 1m 1.5k 1uf i l r2 l dcr r1 c i l +- v c
rt8800/b 18 ds8800/b-08 april 2011 www.richtek.com r icommon2 85.8k choose r icommon2 = 82k assume the negative inductor valley current is ? 5a at no load, then for r icommon1 = 330 , r ad j = 160 , v out = 1.300 icommon1 l icommon2 l icommon2 out icommon1 l icommon2 l out icommon1 l icommon2 icommon x r dcr i r dcr i r v r dcr i r dcr i v r dcr i r v i + + = + + = + = icommon1 l icommon2 icommon r dcr i r v 330 1m 5a r 1.3v icommon2 - if gm holds input voltages equal, then v ispx = v icommon for the lack of sinking capability of gm, r icommon2 should be small enough to compensate the negative inductor valley current especially at light loads. for load line design, with application circuit in figure 15, it can eliminate the dead zone of load line at light loads. v ispx = v out +i l x dcr figure 15. application circuit of gm current balance rt8800/b senses the inductor current via inductor ? s dcr for channel current balance and droop tuning. the differential sensing gm amplifier converts the voltage on the sense component (can be a sense resistor or the dcr of the inductor) to current signal into internal balance circuit. the current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. if the current of some power channel is larger than average, the balancing signal reduces that channels pulse width to keep current balance. the use of single gm amplifier via time sharing technique to sense all inductor currents can reduce the offset errors and linearity variation between gms. thus it can greatly improve signal processing especially when dealing with such small signal as voltage drop across dcr. voltage reference for converter output & load droop the positive input of error amplifier is pi pin that sinks current proportional to the sum of converter output current. v drp = 2i sink x r drp . the load droop proportional to load current can be set by the resistor between pi pin & external v dacq produced by either buffer amplifier or other voltage source. the pi pin voltage should be larger than 0.8v for good droop circuit performance. figure 16 load line without dead zone at light loads 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.3 1.31 0 5 10 15 20 25 i out (a) v core (v) r icommom2 open r icommon2 = 82k l dcr esr r icommon1 gmx ix + - r icommon2 v ispx v icommon v c c +-
rt8800/b 19 ds8800/b-08 april 2011 www.richtek.com dac offset voltage tuning the intel specification requires that at no load the nominal output voltage of the regulator be offset to a value lower than the nominal voltage corresponding to the v id code. the offset is tuning from rg in the dac generator as figure 18. if vid0~6 is set at vss (ground), and to suppose that shunt resistance is rs. from below equation, we can tune the value of rg to increase or decrease the base voltage of v dacq . ref s f ref g f dacq x v r r x v ) r r (1 v + + = + - v ref (0.8v) vdacfb op vdacq rf rg vid0 vid1 vid2 vid3 vid4 vid5 r r r r r r figure 18. the structure of discrete dac generator over current protection ocp comparator co\mpares each inductor current sensed & sample/hold by current sense circuit with this reference current(150ua). rt8800/b uses hiccup mode to eliminate fault detection of ocp or reduce output current when output is shorted to ground. figure 19. the over current protection in the interval ch1:(5v/div) ch2:(5v/div) over current protection time (25ms/div) pwm i l figure 20. over current protection at steady state ch1:(5v/div) ch2:(5v/div) over current protection time (25ms/div) pwm v ss fault detection the ? hiccup mode ? operation of over current protection is adopted to reduce the short circuit current. the in-rush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage by an internal slow rising ramp. figure 17. load droop circuit ea fb pi +- + - v dacq v drp 2xi x1 2xi x2 2xi x3 i sink
rt8800/b 20 ds8800/b-08 april 2011 www.richtek.com design procedure suggestion a.output filter pole and zero (inductor, output capacitor value & esr). b.error amplifier compensation & sawtooth wave amp- litude (compensation network). current loop setting a.gm amplifier s/h current (current sense component dcr, icommon pin external resistor value). b.over-current protection trip point (r icommon1 resistor). vrm load line setting a.droop amplitude (pi pin resistor). b.no load offset (r icommon2 ) power sequence & ss dvd pin external resistor and ss pin capacitor. pcb layout a.sense for current sense gm amplifier input. b.refer to layout guide for other items. voltage loop setting design example given: apply for four phase converter v in = 12v v core = 1.5v i load(max) = 100a v droop = 100mv at full load (1m load line) ocp trip point set at 35a for each channel (s/h) dcr = 1m of inductor at 25 c l = 1.5 h c out = 8000 f with 5m equivalent esr. figure 21. type 2 compensation network of ea 2. over-current protection setting consider the temperature coefficient of copper 3900ppm/ c, ea rb2 rb1 + - 15k c1 12nf c2 68pf 4.7k 1. compensation setting a. modulator gain, pole and zero: from the following formula: modulator gain =v in /v ramp =12/2.4=5 (i.e 14db) where v ramp : ramp amplitude of saw-tooth wave 35.6a i a 150 330 1.39m i a 150 r dcr i l l icommon1 l = = = lc filter pole = 1.45khz and esr zero =3.98khz b. ea compensation network: select r1 = 4.7k, r2 = 15k, c1 = 12nf, c2 = 68pf and use the type 2 compensation scheme shown in figure 21. by calculation, the f z = 0.88khz, f p = 322khz and middle band gain is 3.19 (i.e 10.07db).
rt8800/b 21 ds8800/b-08 april 2011 www.richtek.com layout considerations place the high-power switching components first, and separate them from sensitive nodes. 1. most critical path: the current sense circuit is the most sensitive part of the converter. the current sense resistors tied to isp1,2,3 and icommon should be located not more than 0.5 inch from the ic and away from the noise switching nodes. the pcb trace of sense nodes should be parallel and as short as possible. r&c filter of choke should place close to pwm and the r & c connect directly to the pin of each output choke, use 10 mil differencial pair, and 20 mil gap to other phase pair. less via as possible. figure 22. power stage ripple current path sw2 l2 sw1 l1 c out r l v out v in r in c in v 2. switching ripple current path: a. input capacitor to high side mosfet. b. low side mosfet to output capacitor. c. the return path of input and output capacitor. d. separate the power and signal gnd. e. the switching nodes (the connection node of high/ low side mosfet and inductor) is the most noisy points. keep them away from sensitive small-signal node. f . reduce parasitic r, l by minimum length, enough copper thickness and avoiding of via. 3. mosfet driver should be closed to mosfet.
rt8800/b 22 ds8800/b-08 april 2011 www.richtek.com figure 23. layout consideration figure 24 pwm rt pi vcc comp fb rt8800/b cspx +5v in c bp c c r icom c out r c r fb next to ic locate next to fb pin l o1 v core c in locate near mosfets c boot +12v or +5v 0.1uf +12v vcc in gnd bst drvh sw drvl rt9603 next to ic gnd gnd icommon r drd
rt8800/b 23 ds8800/b-08 april 2011 www.richtek.com figure 25 figure 26
rt8800/b 24 ds8800/b-08 april 2011 www.richtek.com figure 27
rt8800/b 25 ds8800/b-08 april 2011 www.richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2
rt8800/b 26 ds8800/b-08 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com f b c i h d a j m dimensions in millimeters dimensions in inches symbol min max min max a 9.804 10.008 0.386 0.394 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.178 0.254 0.007 0.010 i 0.102 0.254 0.004 0.010 j 5.791 6.198 0.228 0.244 m 0.406 1.270 0.016 0.050 16 ? lead sop plastic package

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